1. Field of the Invention
This invention relates to a memory device, and more particularly to a ferroelectric memory device in which a switching transistor is coupled to a plurality of ferroelectric capacitors, thereby outputting a plurality of information when an address signal is inputted.
2. Description of the Prior Art
It is well known that the ferroelectric memory element has been gaining importance as a next generation memory since it has non-volatile characteristics. The memory including a plurality of ferroelectric material can be a non-volatile memory by using the characteristics that maintain a constant charge amount for the ferroelectric material characteristics even if the potential difference in both ends of a capacitor does not exist.
FIG. 1A shows a symbol of a ferroelectric capacitor, and FIG. 1B is a graph showing the charge amount vs voltage curve where the ferroelectric capacitor has a hysterisis relationship between the voltage and the charge. As shown in the hysterisis curve, even if the voltage in both ends of a capacitor is 0V, binary information can be memorized since the constant charge amount is maintained as a state "P1" or "P2", unlike linear capacitors. This is due to the fact that the atomic arrangement of the ferroelectric material is polarized when the electric field is applied to and cut off from the ferroelectric material. This is the very reason that the memory used by the ferroelectric capacitor as a storage means, can be a non-volatile memory. Another feature of the ferroelectric capacitor is that the charge amount curve according to the voltage or potential has a hysterisis relationship. Any voltage which is lower than -3V is applied to the ferroelectric capacitor, the polarization state of the ferroelectric material is changed and then the charge amount is moved to state "P3" as depicted in FIG.1B. While the minus voltage is changed to plus voltage, the charge amount is moved to state "P4" through state "P2". Thus, the charge amount for the ferroelectric capacitor is changed along with arrow direction in accordance with the voltage variation as depicted by the arrow direction in FIG. 1B.
There are many cases wherein the ferroelectric capacitors are applied to the memory elements. A ferroelectric memory cell generally includes one witching transistor and one dielectric capacitor. Also, a memory array having a plurality of memory cell includes a plurality of word lines for driving each switching transistor and bit lines for sensing and amplifying the charge amount stored in capacitors. Each word line and bit line is connected so that they cross each other. Each word line is connected to the gate of each switching transistor to control the switching on/off operation, each bit line is connected to a source of each switching transistor, and one end of each dielectric capacitor is connected to a drain of each switching transistor, respectively. The other end of the electric capacitor is connected to each plate line, respectively. In order to detect or store the charge which is stored in a dielectric capacitor in the ferroelectric memory element, an electric field is applied to both ends of each capacitor.
FIG. 2 is a circuit diagram showing a related ferroelectric memory device including a switching transistor and a dielectric capacitor. Here, one bit information of "0" or "1" digit is stored in the capacitor. But, an address signal is generally applied to the memory device, and a plurality of output signals, (i.g. 1,8,16,32, . . . etc.) are outputted by driving switching transistors corresponding to the number of the output signals. For example, if a memory device, which is set to output 8 bits (i.e. 1 byte) at a certain time, is accessed by an input address, 8 switching transistors are turned on in order to output the corresponding data. However, as the memory device requires a large numner of output data, the level of the circuit complexity may be highly increased in proportion to the number of the switching transistors. Accordingly, there are problems including the increase of power consumption and the enlargement of the total chip area of the memory device which leads to further circuit complexity.